Title :
Early prediction of NBTI effects using RTL source code analysis
Author :
Kumar, Jayanand Asok ; Butler, Kenneth M. ; Kim, Heesoo ; Vasudevan, Shobha
Author_Institution :
Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
In present day technology, the design of reliable systems must factor in temporal degradation due to aging effects such as Negative Bias Temperature Instability (NBTI). In this paper, we present a methodology to estimate delay degradation early at the Register Transfer Level (RTL). We statically analyze the RTL source code to determine signal correlations. We then determine probability distributions of RTL signals formally by using probabilistic model checking. Finally, we propagate these signal probabilities through delay macromodels and estimate the delay degradation. We demonstrate our methodology on several benchmarks RTL designs. We estimate the degradation with <;10% error and up to 18.2× speedup in runtime as compared to estimation using gate-level simulations.
Keywords :
MOSFET; circuit simulation; correlation methods; formal verification; integrated circuit design; integrated circuit reliability; statistical analysis; statistical distributions; PMOS transistors; RTL source code analysis; aging effects; circuit simulations; delay degradation estimation; delay macromodels; early NBTI effect prediction; gate-level simulations; negative bias temperature instability; probabilistic model checking; probability distributions; register transfer level; reliable system design; signal correlation; signal probabilities; statistical analysis; Aging; Computational modeling; Degradation; Delay; Logic gates; Probabilistic logic; Reliability; Aging; NBTI; RTL; Static Analysis; Statistical Analysis;
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4503-1199-1