• DocumentCode
    565227
  • Title

    Hybrid DRAM/PRAM-based main memory for single-chip CPU/GPU

  • Author

    Kim, Dongki ; Lee, Sungkwang ; Chung, Jaewoong ; Kim, Dae Hyun ; Woo, Dong Hyuk ; Yoo, Sungjoo ; Lee, Sunggu

  • fYear
    2012
  • fDate
    3-7 June 2012
  • Firstpage
    888
  • Lastpage
    896
  • Abstract
    Single-chip CPU/GPU architecture is being adopted in high-end (embedded) systems, e.g., smartphones and tablet PCs. Main memory subsystem is expected to consist of hybrid DRAM and phase-change RAM (PRAM) due to the difficulties in DRAM scaling. In this work, we address the performance optimization of the hybrid DRAM/PRAM main memory for single chip CPU/GPU. Based on the tight requirements of low latency from CPU and the relative tolerance to long latency from GPU, DRAM is first allocated to CPU while PRAM with longer write latency is allocated to GPU. Then, in order to improve the write performance of GPU traffic, we propose (1) an in-DRAM write buffer to accommodate GPU write traffics, (2) dynamic hot data management to improve the efficiency of write buffer, (3) runtime-adaptive adjustment of write buffer size to meet the given CPU performance bound, and (4) CPU-aware DRAM access scheduling to give low latency to CPU traffics. The experiments show that the proposed method gives 1.02~44.2 times performance improvement in GPU performance with modest (negligible) CPU performance overhead (when compute-intensive CPU programs run).
  • Keywords
    DRAM chips; buffer storage; embedded systems; graphics processing units; memory architecture; performance evaluation; phase change memories; processor scheduling; CPU performance bound; CPU performance overhead; CPU-aware DRAM access scheduling; DRAM scaling; DRAM/PRAM-based main memory; GPU write traffics; compute-intensive CPU program run; dynamic hot data management; embedded systems; graphics processing units; in-DRAM write buffer; performance optimization; phase-change RAM; relative tolerance; runtime-adaptive adjustment; single-chip CPU/GPU architecture; smart phones; tablet PC; write buffer efficiency improvement; write buffer size; write latency; write performance improvement; Bandwidth; Graphics processing unit; Memory management; Phase change random access memory; Runtime; Main memory subsystem; phase-change RAM; single-chip CPU/GPU;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
  • Conference_Location
    San Francisco, CA
  • ISSN
    0738-100X
  • Print_ISBN
    978-1-4503-1199-1
  • Type

    conf

  • Filename
    6241609