Title :
Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors
Author :
Jiang, Lei ; Zhao, Bo ; Zhang, Youtao ; Yang, Jun
Author_Institution :
Electr. & Comput. Eng. Dept., Univ. of Pittsburgh, Pittsburgh, PA, USA
Abstract :
MLC STT-MRAM (Multi-level Cell Spin-Transfer Torque Magnetic RAM), an emerging non-volatile memory technology, has become a promising candidate to construct L2 caches for high-end embedded processors. However, the long write latency limits the effectiveness of MLC STT-MRAM based L2 caches. In this paper, we address this limitation with two novel designs: Line Pairing (LP) and Line Swapping (LS). LP forms fast cachelines by re-organizing MLC soft bits which are faster to write. LS dynamically stores frequently written data into these fast cachelines. Our experimental results show that LP and LS improve system performance by 15% and reduce energy consumption by 21%.
Keywords :
MRAM devices; cache storage; MLC soft bits; cache; cell spin-transfer torque magnetic RAM; energy consumption; high-end embedded processor; line pairing; line swapping; multilevel cell STT-MRAM; nonvolatile memory technology; write latency limit; Arrays; Benchmark testing; Energy consumption; Magnetic tunneling; Program processors; Random access memory; Switches; LLC; MLC; STT-MRAM;
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4503-1199-1