DocumentCode :
565240
Title :
Regaining throughput using completion detection for error-resilient, near-threshold logic
Author :
Crop, Joseph ; Pawlowski, Robert ; Chiang, Patrick
Author_Institution :
Oregon State Univ., Corvallis, OR, USA
fYear :
2012
fDate :
3-7 June 2012
Firstpage :
974
Lastpage :
979
Abstract :
Operating in the near-threshold regime can result in significant energy savings. Unfortunately, the increased timing variation prevents conventional error-detection techniques from properly functioning. This paper introduces two circuit-level timing error detection techniques that aim to increase throughput while operating in the near-threshold voltage regime: current-sensing completion detection and transition-aware completion detection. Each method allows any digital circuit to operate at speeds not limited by the worst-case critical path. Throughput improvements and energy savings are reported for implementations on a 16-bit adder.
Keywords :
adders; error detection; threshold logic; adder; circuit level timing error detection techniques; completion detection; current sensing completion detection; digital circuit; energy savings; error resilient near-threshold logic; near-threshold voltage regime; transition aware completion detection; word length 16 bit; worst case critical path; Adders; Clocks; Delay; Logic gates; Noise; Throughput; Completion Detection; Error Detection; Low Power; Variation Tolerance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
ISSN :
0738-100X
Print_ISBN :
978-1-4503-1199-1
Type :
conf
Filename :
6241622
Link To Document :
بازگشت