Title :
Can pin access limit the footprint scaling?
Author :
Xiang Qiu ; Marek-Sadowska, M.
Author_Institution :
Univ. of California Santa Barbara, Santa Barbara, CA, USA
Abstract :
If pin density exceeds a certain threshold, pin access becomes a challenge for inter-cell signal routing and increasing the number of metal layers cannot improve routability. CMOS and FinFET layouts may never reach this threshold, but Vertical Slit Field Effect Transistor (VeSFET) ICs may exceed it. We demonstrate that VeSFET layouts are still routable within footprint using two-sided routing which achieves better wire length and via usage than one-sided routing with or without white space inserted.
Keywords :
CMOS integrated circuits; VLSI; field effect transistors; integrated circuit layout; network routing; scaling circuits; CMOS; FinFET layout; VeSFET IC; VeSFET layout; footprint scaling; intercell signal routing; metal layer; pin density; routability; vertical slit field effect transistor; Layout; Metals; Pins; Routing; Transistors; White spaces; Wires; Detailed routing; VeSFET; net partitioning; pin density; two-sided routing;
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4503-1199-1
