DocumentCode
565265
Title
Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse
Author
Taylor, Michael Bedford
Author_Institution
Comput. Sci. & Eng. Dept., Univ. of California, San Diego, CA, USA
fYear
2012
fDate
3-7 June 2012
Firstpage
1131
Lastpage
1136
Abstract
Due to the breakdown of Dennardian scaling, the percentage of a silicon chip that can switch at full frequency is dropping exponentially with each process generation. This utilization wall forces designers to ensure that, at any point in time, large fractions of their chips are effectively dark or dim silicon, i.e., either idle or significantly underclocked. As exponentially larger fractions of a chip´s transistors become dark, silicon area becomes an exponentially cheaper resource relative to power and energy consumption. This shift is driving a new class of architectural techniques that “spend” area to “buy” energy efficiency. All of these techniques seek to introduce new forms of heterogeneity into the computational stack. We envision that ultimately we will see widespread use of specialized architectures that leverage these techniques in order to attain orders-of-magnitude improvements in energy efficiency. However, many of these approaches also suffer from massive increases in complexity. As a result, we will need to look towards developing pervasively specialized architectures that insulate the hardware designer and the programmer from the underlying complexity of such systems. In this paper, I discuss four key approaches - the four horsemen - that have emerged as top contenders for thriving in the dark silicon age. Each class carries with its virtues deep-seated restrictions that requires a careful understanding of the underlying tradeoffs and benefits.
Keywords
computational complexity; electric breakdown; elemental semiconductors; energy conservation; integrated circuit design; power aware computing; silicon; Dennardian breakdown scaling; Dim silicon; Si; architectural technique; chip transistor; complexity; computational stack; dark silicon; energy consumption; energy efficiency; power consumption; process generation; silicon chip; utilization wall; Complexity theory; Hardware; Multicore processing; Program processors; Silicon; Transistors; Dark Silicon; Dennardian Scaling; Dim Silicon; Multicore; Near Threshold; Specialization; Utilization Wall;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location
San Francisco, CA
ISSN
0738-100X
Print_ISBN
978-1-4503-1199-1
Type
conf
Filename
6241647
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