Title :
Platform 2012, a many-core computing accelerator for embedded SoCs: Performance evaluation of visual analytics applications
Author :
Melpignano, Diego ; Benini, Luca ; Flamand, Eric ; Jego, Bruno ; Lepley, Thierry ; Haugou, Germain ; Clermidy, Fabien ; Dutoit, Denis
Author_Institution :
AST, STMicroelectron., Grenoble, France
Abstract :
P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters. Each cluster features up to 16 processors with independent instruction streams sharing a multi-banked one-cycle access L1 data memory, a multi-channel DMA engine and specialized hardware for synchronization and aggressive power management. P2012 is 3D stacking ready and can be customized to achieve extreme area and energy efficiency by adding domain-specific HW IPs to the cluster. The first P2012 SoC prototype in 28nm CMOS will sample in Q3, featuring four 16-processor clusters, a 1MB L2 memory and delivering 80GOPS (with 32 bit single precision floating point support) in 18mm2 with 2W power consumption (worst-case). P2012 can run standard OpenCL™ and proprietary Native Programming Model SW components to achieve the highest level of control on application-to-resource mapping. A dedicated version of the OpenCV vision library is provided in the P2012 SW Development Kit to enable visual analytics acceleration. This paper will discuss preliminary performance measurements of common feature extraction and tracking algorithms, parallelized on P2012, versus sequential execution on ARM CPUs.
Keywords :
CMOS memory circuits; embedded systems; energy conservation; feature extraction; file organisation; microprocessor chips; multiprocessing systems; parallel architectures; performance evaluation; power aware computing; synchronisation; system-on-chip; 16-processor clusters; 3D stacking; ARM CPU; CMOS; L2 memory; OpenCV vision library; P2012; P2012 SW Development Kit; P2012 SoC prototype; application-to-resource mapping; area-efficient many-core computing accelerator; domain-specific HW IP; embedded SoC; energy efficiency; feature extraction; instruction streams; multibanked one-cycle access L1 data memory; multichannel DMA engine; multiple globally asynchronous locally synchronous processor clusters; native programming model; performance evaluation; performance measurements; power 2 W; power management; power-efficient many-core computing accelerator; sequential execution; size 28 nm; synchronization; tracking algorithms; visual analytics applications; Acceleration; Computer architecture; Fabrics; Hardware; Programming; Software; System-on-a-chip; 3D stacking; Low-power; SoC; computer vision; feature extraction; many-core; process aware;
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4503-1199-1
