Title :
Exploiting narrow-width values for process variationtolerant 3-D microprocessors
Author :
Kong, Joonho ; Chung, Sung Woo
Author_Institution :
Dept. of Comput. & Radio Commun. Eng., Korea Univ., Seoul, South Korea
Abstract :
Process variation is a challenging problem in 3D microprocessors, since it adversely affects performance, power, and reliability of 3D microprocessors, which in turn results in yield losses. In this paper, we propose a novel architectural scheme that exploits the narrow-width value for yield improvement of last-level caches in 3D microprocessors. In a energy-/performance-efficient manner, our proposed scheme improves cache yield by 58.7% and 17.3% compared to the baseline and the naïve way-reduction scheme (that simply discards faulty cache lines), respectively.
Keywords :
cache storage; energy conservation; integrated circuit reliability; losses; microprocessor chips; three-dimensional integrated circuits; 3D microprocessors performance; 3D microprocessors reliability; energy-efficient manner; last-level caches; naive way-reduction scheme; narrow-width value; narrow-width values; process variation-tolerant 3D microprocessors; Arrays; Delay; Energy consumption; Logic gates; Microprocessors; Random access memory; Routing; 3D microprocessor; Last-level cache; Narrow-width value; Process variation; Yield;
Conference_Titel :
Design Automation Conference (DAC), 2012 49th ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4503-1199-1
