DocumentCode
56608
Title
Novel Vertical SOI-Based 1T-DRAM With Trench Body Structure
Author
Jyi-Tsong Lin ; Po-Hsieh Lin ; Yi-Chuen Eng ; Yun-Ru Chen
Author_Institution
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Volume
60
Issue
6
fYear
2013
fDate
Jun-13
Firstpage
1872
Lastpage
1877
Abstract
A vertical silicon-on-insulator (VSOI)-based capacitorless 1T-DRAM cell with a trench body structure is proposed. The trench body is added as an additional neutral region under the device channel region through a self-aligned fabrication process in a 300 nm wide VSOI MOSFET that enables the device to separate the hole storage region and sense electron current region without extra area penalty. With the holes stored in the trench body, the floating-body effect occurs and affects the threshold voltage significantly. A Synopsys TCAD software tool is also used to evaluate the device performance for DC and transient analysis. The electrical and transient characteristics confirm how the proposed device with trench body can be used perfectly as a 1T-DRAM application to achieve desirable performance in terms of a larger programming window and longer retention time.
Keywords
DRAM chips; silicon-on-insulator; technology CAD (electronics); transient analysis; DC analysis; Synopsys TCAD software tool; VSOI MOSFET; device channel region; electrical characteristics; floating-body effect; hole storage region; neutral region; programming window; retention time; self-aligned fabrication process; sense electron current region; size 300 nm; threshold voltage; transient analysis; trench body structure; vertical silicon-on-insulator-based capacitorless 1T-DRAM cell; Capacitorless 1T-DRAM; silicon-on-insulator technology; trench body structure;
fLanguage
English
Journal_Title
Electron Devices, IEEE Transactions on
Publisher
ieee
ISSN
0018-9383
Type
jour
DOI
10.1109/TED.2013.2259171
Filename
6515197
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