TSV optimization for BEOL interconnection in logic process

Author

Kang, Sinwoo ; Cho, Sungdong ; Yun, Kiyoung ; Ji, Sangwook ; Bae, Kisoon ; Lee, Woonseob ; Kim, Eunji ; Kim, Jangho ; Cho, Jonghoon ; Mun, Hyongyol ; Park, Yeong L.

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

4

Abstract

Control of Cu extrusion and delamination due to CTE mismatch between Si and Cu is a big issue for high reliable TSV formation. In this paper we tried to find some methods to reduce Cu extrusion and to prevent TSV sidewall delamination. It is demonstrated that residual Cu extrusion height can be reduced by additional high temperature heat treatment before TSV CMP. And also Cu extrusion and delamination strongly depends on TSV dimension, which leads to the conclusion that smaller vias are preferred for better reliability.

Keywords

chemical mechanical polishing; copper; delamination; elemental semiconductors; heat treatment; integrated circuit interconnections; silicon; three-dimensional integrated circuits; BEOL interconnection; CTE mismatch; Cu; Si; TSV CMP; TSV optimization; TSV sidewall delamination; coefficient of thermal expansion; high reliable TSV formation; high temperature heat treatment; logic process; residual copper extrusion height; through silicon vias; Delamination; Heat treatment; Resistance; Silicon; Stress; Thermal stresses; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6262947

Filename

6262947