Comparative study of side-wall roughness effects on leakage currents in through-silicon via interconnects

Author

Nakamura, Tomoji ; Kitada, Hideki ; Mizushima, Yoriko ; Maeda, Nobuhide ; Fujimoto, Koji ; Ohba, Takayuki

Author_Institution

Fujitsu Labs. Ltd., Atsugi, Japan

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

4

Abstract

Influence of the sidewall roughness in through-silicon via (TSV) on leakage currents has been studied. Micro steps along the sidewall, so-called scalloping, formed by Bosch etching, are strongly related to leakage currents between adjacent TSVs. Microcracks in the SiON barriers were observed by TEM analysis and correlated with the sidewall roughness. FEM simulations of the stress concentration along the sidewall roughness clarified the origin of cracking. A non-Bosch etching process showed smooth sidewall surface and we consider it to be feasible for reliable TSV interconnects.

Keywords

etching; finite element analysis; integrated circuit interconnections; leakage currents; microcracks; silicon compounds; three-dimensional integrated circuits; transmission electron microscopy; FEM simulations; SiON; TEM analysis; TSV interconnects; leakage currents; microcracks; nonBosch etching process; scalloping; side-wall roughness effects; stress concentration; through-silicon via interconnects; Annealing; Dielectrics; Etching; Films; Leakage current; Stress; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6262948

Filename

6262948