Author :
Druais, G. ; Ancey, P. ; Aumont, C. ; Caubet, V. ; Chapelon, L.-L. ; Chaton, C. ; Cheramy, S. ; Cordova, S. ; Cirot, E. ; Colonna, J. -P ; Coudrain, P. ; Divel, T. ; Dodo, Y. ; Farcy, A. ; Guitard, N. ; Haxaire, K. ; Hotellier, N. ; Leverd, F. ; Liou, R.
Abstract :
3D integration has now made a place in semiconductor landscape and is coming closer from implementation in manufacturing. Although process bricks are almost all available now, there are still several challenges to solve before it is introduced in standard flows. One of those which is not commonly addressed is to get final customer´s interest by showing him evaluations and results on real industrial applications. Heterogeneous integration and the possibility to partition different functions of a product in separate layers is one of the advantages of 3D integration. In this paper, product partitioning with TSV and 3D integration is demonstrated without inducing any impact on final product functionality and on early package level reliability tests.
Keywords :
integrated circuit design; integrated circuit packaging; integrated circuit reliability; integrated circuit testing; three-dimensional integrated circuits; 3D integration demonstration; TSV integration; design partitioning; package level reliability tests; product partitioning; semiconductor landscape; wireless product; Assembly; Bonding; Copper; Packaging; Standards; Through-silicon vias; 3DIC; TSV; copper pillars; partitioning; stacking;
