Supply current testing of open defects at interconnects in 3D Ics with IEEE 1149.1 architecture

Author

Konishi, Tomoaki ; Yotsuyanagi, Hiroyuki ; Hashizume, Masaki

Author_Institution

Inst. of Technol. & Sci., Univ. of Tokushima, Tokushima, Japan

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

6

Abstract

In this paper, a supply current test method of 3D ICs is proposed to detect open defects occurring at interconnects between two dies in which IEEE 1149.1 architecture is implemented and locate the defective interconnects. Also, a testable design method is proposed for the test method and a testable designed IC is prototyped. Furthermore, testability of the test method is evaluated by some experiments with the prototyped IC and by Spice simulation. The simulation results show that an open defect can be detected within 10nsec which generates only additional delay of 0.7nsec.

Keywords

IEEE standards; SPICE; integrated circuit design; integrated circuit interconnections; integrated circuit testing; three-dimensional integrated circuits; 3D IC interconnects; IEEE 1149.1 architecture; Spice simulation; defective interconnects; open defects detection; supply current testing; testable IC design; testable design method; time 10 ns; Delay; Electrostatic discharges; Integrated circuit interconnections; Integrated circuit modeling; Resistors; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6262968

Filename

6262968