• DocumentCode
    566243
  • Title

    High density Cu-TSVs and reliability issues

  • Author

    Mariappan, Murugesan ; Kobayashi, Harufumi ; Fukushima, Takafumi ; Tanaka, Tetsu ; Koyanagi, Mitsumasa

  • Author_Institution
    New Ind. Creation Hatchery Center (NICHe), Tohoku Univ., Sendai, Japan
  • fYear
    2012
  • fDate
    Jan. 31 2012-Feb. 2 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Reliability issues such as thermo-mechanical stress, extrusion of via metal, and die-cracking caused by high density Cu-TSVs in 3D-LSI Si die/wafer after wafer thinning and bonding have been systematically investigated respectively using micro-Raman spectroscopy, laser microscopy, and optical microscopy techniques. It is inferred that (i) for the TSV pitch value of less than twice the TSV-width, the remnant stress present in the Si at the TSV space region is turned to be only compressive, i.e. in the lateral direction, the compressive stress produced by the adjacent TSVs overlapped to each other; for the TSV pitch values of greater than two times the TSV-width, the compressive stress in the Si at the vicinity of TSV is followed by the tensile stress and beyond that it becomes stress free at the TSV space region; (ii) Irrespective of the TSV shape and size, the lateral extrusion of Cu occurs at the TSV space region. The lateral extrusion becomes prominent for the larger TSV size values and the higher bonding temperatures. The lateral extrusion is larger for the 20 μm-width TSV annealed at the higher temperature (~4 μm @ 400 °C) than for the TSV annealed at lower temperature (a maximum of only 1.5 μm @ 200 °C); (iii) Cracking of LSI die/wafer occurs at the periphery of the TSV array for very fine pitch values, and for larger pitch values cracking occurs in between TSVs.
  • Keywords
    fine-pitch technology; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; large scale integration; three-dimensional integrated circuits; wafer bonding; 3D-LSI; Cu; TSV pitch value; TSV space region; compressive stress; die cracking; fine pitch values; laser microscopy; lateral extrusion; micro-Raman spectroscopy; optical microscopy; reliability issues; temperature 200 degC; temperature 400 degC; thermo-mechanical stress; through silicon vias; via metal; wafer bonding; wafer thinning; Annealing; Arrays; Bonding; Large scale integration; Silicon; Stress; Through-silicon vias;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    3D Systems Integration Conference (3DIC), 2011 IEEE International
  • Conference_Location
    Osaka
  • Print_ISBN
    978-1-4673-2189-1
  • Type

    conf

  • DOI
    10.1109/3DIC.2012.6262969
  • Filename
    6262969