• DocumentCode
    566251
  • Title

    Selection of underfill material in Cu hybrid bonding and its effect on the transistor keep-out-zone

  • Author

    Lim, D.F. ; Leong, K.C. ; Tan, C.S.

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
  • fYear
    2012
  • fDate
    Jan. 31 2012-Feb. 2 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Hybrid bonding of Cu with PECVD oxide (PE-TEOS), benzocyclobutane (BCB), and polyimide (PI) is gaining importance in third dimensional IC fabrication. Thermal mechanical simulation is performed on Cu hybrid bonding structure as the gap-filling materials are not thermally matched to the back-end-of-line (BEOL) materials. Two bonded Si layer connected by TSV with different underfill materials are compared with metal bonding without underfill. Stress profile in the Si substrate for back-to-face and face-to-face bonding orientations is extracted. By using the piezoresistive equation, keep-out-zone (KOZ) for MOS transistor is estimated. TEOS is found to be able to minimize the mobility change for n-MOSFET but similar effect is not observed in p-MOSFET. Mobility change when organic polymer (BCB or PI) underfill is used shows dependency on the via diameter and channel orientation. This study provides a guideline for transistor placement in hybrid bonding to minimize mobility change.
  • Keywords
    MOSFET; bonding processes; copper; elemental semiconductors; integrated circuit interconnections; plasma CVD; silicon; three-dimensional integrated circuits; BEOL; Cu; MOS transistor; PE-TEOS; PECVD oxide; Si; TSV; back-end-of-line materials; back-to-face bonding orientation; benzocyclobutane; bonding structure; channel orientation; face-to-face bonding orientation; gap filling materials; hybrid bonding; mobility change; n-MOSFET; organic polymer; p-MOSFET; piezoresistive equation; polyimide; stress profile; thermal mechanical simulation; third dimensional IC fabrication; through silicon vias; transistor keep-out-zone; transistor placement; underfill material;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    3D Systems Integration Conference (3DIC), 2011 IEEE International
  • Conference_Location
    Osaka
  • Print_ISBN
    978-1-4673-2189-1
  • Type

    conf

  • DOI
    10.1109/3DIC.2012.6262981
  • Filename
    6262981