Minimization of the local residual stress in 3DICs by controlling the structures and mechanical properties of 3D interconnections

Author

Nakahira, Kota ; Endo, Fumiaki ; Furuya, Ryosuke ; Suzuki, Ken ; Miura, Hideo

Author_Institution

Fracture & Reliability Res. Inst., Tohoku Univ., Sendai, Japan

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

6

Abstract

Since the residual stress in a silicon chip mounted in 3D modules causes the degradation of both electrical and mechanical reliability, the dominant factors of the residual stress was investigated by using a finite element method and experiments applying 2-μm long piezoresistance strain gauges. The residual stress and local deformation of the chip were found to vary drastically depending on the mechanical properties of bumps and underfill and bump alignment structures.

Keywords

deformation; elemental semiconductors; finite element analysis; integrated circuit interconnections; integrated circuit reliability; internal stresses; silicon; three-dimensional integrated circuits; 3D modules; 3DIC; FEM; Si; bump alignment structures; dominant factors; electrical reliability; finite element method; local deformation; local residual stress minimization; mechanical properties; mechanical reliability; piezoresistance strain gauges; silicon chip; size 2 mum; structures properties; underfill; Copper; Residual stresses; Semiconductor device measurement; Silicon; Strain;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6262997

Filename

6262997