A built-in test circuit for open defects at interconnects between dies in 3D ICs

Author

Widianto ; Yotsuyanagi, Hiroyuki ; Ono, Akira ; Takagi, Masao ; Hashizume, Masaki

Author_Institution

Inst. of Technol. & Sci., Univ. of Tokushima, Tokushima, Japan

fYear

2012

fDate

Jan. 31 2012-Feb. 2 2012

Firstpage

1

Lastpage

5

Abstract

In this paper, a built-in test circuit is proposed to detect open defects that occur at interconnects between dies inside 3D ICs. An inverter gate is used in the test circuit as an open sensor. Open defects are detected by means of supply current of the inverter gate flowing when an AC voltage signal is provided to targeted interconnects as a stimulus. The interconnect at which an open defect occurs can be located with the test circuit. Feasibility of tests with the test circuit is examined by circuit simulation. The results promise us that open defects can be detected and also defective interconnects can be located with the test circuit.

Keywords

built-in self test; integrated circuit interconnections; integrated circuit testing; logic gates; three-dimensional integrated circuits; 3D IC; AC voltage signal; built-in test circuit; circuit simulation; interconnect defect; inverter gate; open defect; open defects; open sensor; supply current; CMOS integrated circuits; Circuit faults; Integrated circuit interconnections; Inverters; Logic gates; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

3D Systems Integration Conference (3DIC), 2011 IEEE International

Conference_Location

Osaka

Print_ISBN

978-1-4673-2189-1

Type

conf

DOI

10.1109/3DIC.2012.6263041

Filename

6263041