Title :
Application-specific network-on-chip with link aggregation
Author :
Korotkyi, Ievgen ; Lysenko, Oleksandr
Author_Institution :
Dept. of Design of Electron. Digital Equip., Nat. Tech. Univ. of Ukraine, Kiev, Ukraine
Abstract :
A method is proposed to reduce the hardware costs of networks-on-chip (NoC) with link aggregation by uneven distribution the number of physical links in aggregated logical connections. Created application-specific NoC, hardware costs of which is more than two times lower (by 65%), and the maximum operating frequency is by 41% higher than that of the network with homogeneous architecture. As a result of simulation in ModelSim investigated the transport latencies of the proposed solution.
Keywords :
application specific integrated circuits; circuit simulation; network-on-chip; ModelSim simulation; NoC; aggregated logical connections; application specific network-on-chip; hardware cost reduction; link aggregation; operating frequency; physical links; transport latencies; Switches; Table lookup; LAG; NoC; application specific; link aggregation; network on chip; router; synthesis;
Conference_Titel :
Embedded Computing (MECO), 2012 Mediterranean Conference on
Conference_Location :
Bar
Print_ISBN :
978-1-4673-2366-6
