Superior characteristics and reliability of poly-Si TFTs with vacuum cavities underneath poly-Si gate edges

Poly-Si TFTs with vacuum cavities underneath the poly-Si gate edges (quasi-T gate poly-Si TFTs) were successfully realized by partially wet etching the gate oxide and encapsulating in a vacuum. Because of the vacuum cavity not only as an offset region to reduce the abnormal leakage current in the OFF-state but also as a field-induced drain (FID) to sustain the on-current in the ON-state, the electrical characteristics of the quasi-T gate poly-Si TFTs are superior to the conventional planar poly-Si TFTs. Besides, no matter what static or dynamic electrical stresses, due to the equivalent thicker gate oxide in the offset region, the quasi-T gate poly-Si TFTs accomplish greater reliability than the conventional ones, which is caused by the simultaneous reduction of the vertical and horizontal electric fields near the drain region under bias stressing.