Methodology for Efficient Multi-threading of Parsers in EDA Tools

Parsing of large text files has always been a challenge in commercial EDA tools. These files, typically multiple gigabytes in size, are the channels of communication of intermediate data between point-tools working on different parts of the chip design flow. With the advent of multi-core processors, the core algorithms of the EDA tools have been improving in performance by utilizing this parallelism that is now available. With the performance of the core algorithms improving, the contribution of the time taken to parsing the intermediate data files becomes significant. Hence there is a need to improve the performance of these parsers. We have identified multi-threading as one of the methods to achieve this. The methodology in this paper focuses on identifying and implementing data parallelism. We outline the key ingredients required to implement such parsers and a method to predict the parser runtime even before implementation. Recently, we enhanced two parsers using this methodology and achieved significant performance improvements of 4X on 8-core machines with less than 5% memory degradation.