Optimal transistor sizing and voltage scaling for minimal energy use at fixed performance

Author

Oklobdzija, Vojin G. ; Aktan, Mustafa ; Baran, Dursun

Author_Institution

ACSEL Lab., USA

fYear

2012

fDate

9-10 Aug. 2012

Firstpage

1

Lastpage

10

Abstract

This paper presents a simple sizing method for low-power that is comparable in speed and simplicity to the Logical Effort sizing. Yet, the accuracy of the results is in the range of simulation errors. The method is two orders of magnitude faster than methods based on convex optimization, allowing to make quick design choices and architectural trade-offs. In the standard cell environment the method can reduce power by more than 30% over existing designs obtained using synthesis tools. These results are confirmed on examples implemented in 45nm process.

Keywords

logic design; logic gates; low-power electronics; architectural trade-off; convex optimization; design choice; logical effort sizing; minimal energy use; optimal transistor sizing; simulation errors; size 45 nm; standard cell environment; synthesis tools; voltage scaling; Capacitance; Convex functions; Delay; Integrated circuit modeling; Logic gates; Optimization; Transistors; Design Methodology; Digital Circuit Optimization; Digital Integrated Circuits; Integrated Circuits Modeling; Integrated Circuits Synthesis; Low Power Design; Transistor Sizing; Very Large Scale of Integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Micro-Nanoelectronics, Technology and Applications (EAMTA), 2012 Argentine School of

Conference_Location

Cordoba

Print_ISBN

978-1-4673-2696-4

Type

conf

Filename

6297309