DocumentCode
568820
Title
A generic nonlinear output error structure implemented on a PWL ASIC
Author
Lifschitz, Omar D. ; Agamennoni, Osvaldo
Author_Institution
Dept. de Ing. Electr. y de Computadoras, Univ. Nac. del Sur, Bahía Bianca, Argentina
fYear
2012
fDate
9-10 Aug. 2012
Firstpage
11
Lastpage
16
Abstract
In this paper, we present a Nonlinear Output Error (NOE) model structure implemented on an Application Specific Integrated Circuit (ASIC) chip dedicated to Piecewise Linear (PWL) calculation. Three examples are included to show the performance of the ASIC in quantization, truncation and fixed-point operation. Experimental results and simulation results are shown and compared.
Keywords
application specific integrated circuits; integrated circuit modelling; piecewise linear techniques; NOE model structure; PWL ASIC; application specific integrated circuit chip; fixed-point operation; generic nonlinear output error structure; piecewise linear calculation; quantization; truncation operation; Application specific integrated circuits; Autoregressive processes; Computational modeling; Field programmable gate arrays; MATLAB; Mathematical model; Quantization;
fLanguage
English
Publisher
ieee
Conference_Titel
Micro-Nanoelectronics, Technology and Applications (EAMTA), 2012 Argentine School of
Conference_Location
Cordoba
Print_ISBN
978-1-4673-2696-4
Type
conf
Filename
6297310
Link To Document