An FPGA implementation of a data-bit asynchronous GPS/GLONASS correlator

The design and implementation on an FPGA of a correlation system for the American and Russian Global Positioning Systems (GPS and GLONASS) receivers are presented in this paper. This system permits processing the received signal asynchronously with the data-bits. Typically, in GPS and GLONASS receivers, correlation channels receive the samples in intermediate frequency signal, process them through a phase rotator and correlate them with replicas of the code signals locally generated. Based on these correlations, the receiver synchronizes with the incoming satellite signals, demodulates their data, and calculates its position and its speed. Each correlation channel usually works synchronously with the data-bits of the tracked satellite signal, but asynchronously among themselves. In the proposed system, the correlation channels provide partial correlations before and after the edge of data-bits which permit operating the channels synchronously among themselves, i.e. asynchronously with the data-bits of the signal. This feature brings some advantages for the navigation process because all the measurements are taken simultaneously. The designed system is compatible with the AMBA bus for the communication with an embedded processor and has a number of configurable correlation channels. The most significant aspects of the architecture, which was implemented using the hardware description language VHDL, as well as the obtained results with actual GPS and GLONASS signals are presented.