Simulation-based evolutionary heuristic to sizing an OTA Miller with design centering analysis

The goal of this paper is to present a tool for automatic synthesis of analog basic integrated blocks using the genetic algorithm heuristic and an external electrical simulator. The methodology is based on the minimization of a cost function and a set of constraints in order to size individual transistors of a given circuit. The synthesis methodology is implemented in Matlab and use GAOT (Genetic Algorithm Optimization Toolbox) as heuristic and Synopsys Synopsys HSPICE^® simulator for circuit simulation. As circuit design example, this paper shows the application of the methodology for the design of an OTA Miller in 0.18μm fabrication technology. Monte Carlo simulations are performed in order to analyze yield in the final solution and the importance of the design centering.