An Efficient Tool-Chain for Analyzing Tradeoffs of Code Compression Schemes in Embedded Processors

Code compression has emerged as a promising solution to meet the challenges of rapidly increasing application size and of scarce memory resources in embedded systems. In the past two decades, a large number of compression algorithms have been proposed and implemented to improve overall code density on a wide variety of architectures. However, selecting a code compression/decompression methodology for a target architecture by evaluating the tradeoffs between the compression achievable, the decompression overhead and the hardware cost is a tedious and time consuming task. We address this problem with an efficient tool-chain capable of analyzing different code compression schemes and evaluating the tradeoffs. The tool-chain consists of a front end framework that works with different compression/decompression schemes and a backend with high-level-synthesis and logic-synthesis tools. We have effectively analyzed different compression/decompression schemes of varying complexities using the tool-chain.