Reducing Transistor Variability for High Performance Low Power Chips

CMOS integrated-circuit supply-voltage reduction has plateaued in recent years as increased transistor variability has limited transistor-threshold voltage scaling. The deeply depleted channel transistor, implemented on bulk CMOS, provides a low-cost option to re-enable voltage scaling on both future and legacy CMOS fabrication processes by reducing random variability and providing a strong body factor to pull in systematic variation and compensate for environmental effects resulting in 50 percent lower power at matched performance.