Implementation of AES Algorithm in UART Module for Secured Data Transfer

This work proposes the application of Advanced Encryption Standard (AES) algorithm in Universal Asynchronous Receiver Transmitter (UART) module for secure transfer of data. The proposed architecture implements AES-128 algorithm that encrypts the data before transmission through UART transmitter and decrypts after receiving the data at UART receiver module. In this work, we present the AES-128 encryption and decryption circuit using iterative architecture. The design has a clock generator circuit which provides the different clock frequencies to different sub modules. The complete design is described in Verilog Hardware Description Language (HDL) and is functionally verified using Xilinx ISE 9.1i software. It takes 47.2msec to transmit 128 bit encrypted data and 36.7msec to receive decrypted data on a Xilinx xc2vp70-7ff517 device. All the blocks of the proposed architecture are designed using FPGA technology.