Clock Skew Optimization in Pre and Post CTS

Author

Parthibhan, N. ; Ravi, S. ; Mallikarjun, K.H.

Author_Institution

VIT Univ., Vellore, India

fYear

2012

fDate

9-11 Aug. 2012

Firstpage

146

Lastpage

149

Abstract

The clock distribution is important in all synchronous VLSI Design. The clock skew impacts the performance of synchronous logic circuits. As the scaling moves to nanometer technology, innovative clocking techniques are required to optimize the skew. This is done in backend process of design flow, (i.e.) skew is optimized in Pre and Post CTS. Here tunable clock buffers and tunable clock inverters is designed and it is compared. These designed buffers and inverters are useful for clock skew optimization in pre and post CTS.

Keywords

VLSI; buffer circuits; circuit optimisation; circuit tuning; clocks; integrated circuit design; integrated logic circuits; nanoelectronics; performance evaluation; synchronisation; backend process; clock distribution; clock skew optimization; clock tree synthesis; design flow; innovative clocking techniques; nanometer technology; post CTS; pre-CTS; synchronous VLSI design; synchronous logic circuit performance impacts; tunable clock buffers; tunable clock inverters; Clocks; Delay; Educational institutions; Inverters; Registers; Synchronization; Transistors; CTS (Clock tree synthesis); MDSV (Multi dynamic supply voltage); buffer;

fLanguage

English

Publisher

ieee

Conference_Titel

Advances in Computing and Communications (ICACC), 2012 International Conference on

Conference_Location

Cochin, Kerala

Print_ISBN

978-1-4673-1911-9

Type

conf

DOI

10.1109/ICACC.2012.33

Filename

6305575