Low latency parallel-pipelined configurable FFT-IFFT 128/256/512/1024/2048 for LTE

Long Term Evolution (LTE) is one of the latest technologies in wireless communication field. It has features of higher data rates and low latency. LTE defines a number of channel bandwidths which causes FFT-IFFT in LTE must be configurable. In this paper, we present the efficient implementation of a parallel-pipelined configurable FFT/IFFT processor for Orthogonal Frequency Division Multiple Access (OFDMA) applications in LTE. Proposed architecture combines a multipath delay commutator and single-path delay feedback style to obtain low latency, high throughput, and high efficiency memory. The architecture is implemented in RTL and synthesized in FPGA STRATIX IV EP4SGX530KH40C3. The result reaches maximum frequency 67.28 MHz and 530 clocks latency.