Reliability of circuits under pads for Au and Cu wire bonding

Author

Gambino, J.P. ; Malinowski, J. ; Cote, A. ; Guthrie, B. ; Chapman, P. ; Vize, A. ; Bowe, W. ; Griffin, C. ; Cooney, E. ; Aoki, T. ; Chen, Y. ; Wang, D. ; Jaffe, M.

Author_Institution

IBM Microelectron., Essex Junction, VT, USA

fYear

2012

fDate

2-6 July 2012

Firstpage

1

Lastpage

6

Abstract

The reliability of circuits (wiring and vias) under bond pads has been studied for both Au wire bonding and Cu wire bonding, for bond pads and wiring levels typical of those used in RF technology. Electrical test structures under bond pads were used to characterize wire and via integrity after wire bonding and reliability stresses. In addition, SEM analysis was used to inspect for possible damage to the structures under bond pads after wire bonding. No damage was observed with either electrical testing or with SEM analysis, indicating that it is possible to allow a large variety of layouts under bond pads for both Au wire bonding and Cu wire bonding.

Keywords

circuit reliability; copper; gold; lead bonding; RF technology; SEM analysis; bond pads; circuit reliability; copper wire bonding; electrical test structure; electrical testing; gold wire bonding; reliability stress; via integrity; wiring level; Bonding; Compounds; Gold; Intermetallic; Reliability; Silicon; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2012 19th IEEE International Symposium on the

Conference_Location

Singapore

ISSN

1946-1542

Print_ISBN

978-1-4673-0980-6

Type

conf

DOI

10.1109/IPFA.2012.6306251

Filename

6306251