Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

Author

Dai, Chia-Tsen ; Chiu, Po-Yen ; Ker, Ming-Dou ; Tsai, Fu-Yi ; Peng, Yan-Hua ; Tsai, Chia-Ku

Author_Institution

Inst. of Electron., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2012

fDate

2-6 July 2012

Firstpage

1

Lastpage

4

Abstract

The ESD robustness of gate-driven ESD clamp circuit in a 16-V CMOS process was investigated by the stresses of transmission line pulse (TLP), human-body-model ESD test, and machine-model (MM) ESD test. After TLP stresses of different voltage steps, the same ESD clamp circuit got different secondary breakdown currents (It2). In order to understand such unusual phenomenon, the failure analysis on the TLP-stressed ESD clamp circuits was performed to find the failure mechanism.

Keywords

CMOS integrated circuits; electrostatic discharge; integrated circuit testing; CMOS process; ESD robustness; TLP stress; breakdown current; failure analysis; failure mechanism; gate-driven ESD clamp circuit; human-body-model ESD test; machine-model ESD test; transmission line pulse; voltage 16 V; voltage step; CMOS process; Clamps; Electrostatic discharges; Failure analysis; Logic gates; Stress; Voltage measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits (IPFA), 2012 19th IEEE International Symposium on the

Conference_Location

Singapore

ISSN

1946-1542

Print_ISBN

978-1-4673-0980-6

Type

conf

DOI

10.1109/IPFA.2012.6306283

Filename

6306283