DocumentCode
572420
Title
Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks
Author
Cuesta, Blas ; Ros, Alberto ; Gómez, María E. ; Robles, Antonio ; Duato, José
Author_Institution
Dept. of Comput. Eng., Univ. Politec. de Valencia, Valencia, Spain
fYear
2011
fDate
4-8 June 2011
Firstpage
93
Lastpage
103
Abstract
To meet the demand for more powerful high-performance shared-memory servers, multiprocessor systems must incorporate efficient and scalable cache coherence protocols, such as those based on directory caches. However, the limited directory cache size of the increasingly larger systems may cause frequent evictions of directory entries and, consequently, invalidations of cached blocks, which severely degrades system performance. A significant percentage of the referred memory blocks are only accessed by one processor (even in parallel applications) and, therefore, do not require coherence maintenance. Taking advantage of techniques that dynamically identify those private blocks, we propose to deactivate the coherence protocol for them and to treat them as uniprocessor systems do. The protocol deactivation allows directory caches to omit the tracking of an appreciable quantity of blocks, which reduces their load and increases their effective size. Since the operating system collaborates on the detection of private blocks, our proposal only requires minor modifications. Simulation results show that, thanks to our proposal, directory caches can avoid the tracking of about 57% of the accessed blocks and their capacity can be better exploited. This contributes either to shorten the runtime of parallel applications by 15% while keeping directory cache size or to maintain system performance while using directory caches 8 times smaller.
Keywords
cache storage; distributed shared memory systems; operating systems (computers); performance evaluation; protocols; cached block invalidations; directory cache size; directory entry evictions; high-performance shared-memory servers; multiprocessor systems; operating system; parallel applications; private memory blocks; scalable cache coherence protocol deactivation; system performance degradation; uniprocessor systems; Coherence; Hardware; Memory management; Proposals; Protocols; Vectors; Multiprocessor; cache coherence; coherence deactivation; directory cache; efficiency; operating system; private block;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture (ISCA), 2011 38th Annual International Symposium on
Conference_Location
San Jose, CA
ISSN
1063-6897
Print_ISBN
978-1-4503-0472-6
Type
conf
Filename
6307783
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