The application of bus coding in designing of low power SoC based on Wishbone

System on chip (SoC) is the develop trend of integrated circuit field, and low power design is the hot research point. This paper analyses the designing methods of address and data bus in low power SoC system based on Wishbone. We adapt T0 coding to address bus and BI coding to data bus, which lowers the activity of the bus and the power of SoC effectively. The experimental results show that after these two coding methods are applied in the system, the power reduction is 10%. What´s more, the coding technology combining with gate-controlled clock and power management technology is applied to a H.264 encoding SoC system, resulting in the power reduction of 55%. The experimental results prove that these two bus coding ways can be applied in SoC based on Wishbone bus and low the power effectively.