Evaluation of test algorithms stress effect on SRAMs under neutron radiation

Author

Tsiligiannis, G. ; Dilillo, L. ; Bosio, A. ; Girard, P. ; Todri, A. ; Virazel, A. ; Touboul, A.D. ; Wrobel, F. ; Saigné, F.

Author_Institution

Laboratoired´´Inf. de Robot. et de Microelectron. de Montpellier (LIRMM), Univ. de Montpellier II, Montpellier, France

fYear

2012

fDate

27-29 June 2012

Firstpage

121

Lastpage

122

Abstract

Electronic system reliability over soft errors is very critical as the transistor size shrinks. Many recent works have defined the device error rate under radiation for SRAMs in hold mode (static) and during operation (dynamic). This paper evaluates the impact of running test algorithms on SRAMs exposed to neutron radiation in order to define their stressing factor. The results that we show are based on experiments performed at the TSL facility in Uppsala, Sweden using a Quasi-Monoenergetic neutron beam. The evaluation of the test algorithms is based on the calculated device SEU cross section.

Keywords

SRAM chips; integrated circuit reliability; integrated circuit testing; neutron effects; radiation hardening (electronics); stress effects; SEU cross section device calculation; SRAM; TSL facility; Uppsala Sweden; device error rate; electronic system reliability; neutron radiation exposure; quasimonoenergetic neutron beam; running test algorithm impact evaluation; single event upset; soft error; test algorithm stress effect evaluation; transistor size shrinking; Heuristic algorithms; Neutrons; Particle beams; Random access memory; Single event upset; Stress; Testing; Cross-section; SRAM; Single Event Upset; neutrons; radiation; test;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium (IOLTS), 2012 IEEE 18th International

Conference_Location

Sitges

Print_ISBN

978-1-4673-2082-5

Type

conf

DOI

10.1109/IOLTS.2012.6313853

Filename

6313853