A low-power 18-GHz dual-injection-locked frequency divider in 65-nm CMOS

Author

Huang, Dong ; Diao, Shengxi ; Wei, Peng ; Lin, Fujiang

Author_Institution

Dept. of Electron. Sci. & Technol., Univ. of Sci. & Technol. of China, Hefei, China

fYear

2012

fDate

27-30 May 2012

Firstpage

278

Lastpage

281

Abstract

In this paper, an 18-GHz dual-injection locked frequency divider (ILFD) is presented. In order to decrease the complexity of PLL design, the dual-ILFD doesn´t adopt a frequency adjustment scheme but achieves a large locking range due to fully utilizing the voltage and current injection of the input signal. This ILFD is implemented in SMIC 65nm CMOS technology and consumes 1.8mW from a 1.2V voltage supply excluding buffers and biasing circuits. The core area is 0.35mm× 0.73mm. The measured locking range is 13.3GHz~18.4GHz with 0dBm input power.

Keywords

CMOS analogue integrated circuits; frequency dividers; low-power electronics; microwave integrated circuits; PLL design; SMIC CMOS technology; current injection; dual-ILFD; frequency 13.3 GHz to 18.4 GHz; low power dual-injection-locked frequency divider; power 1.8 mW; size 65 nm; voltage 1.2 V; voltage injection; CMOS integrated circuits; Frequency measurement; Mixers; Oscillators; Switching circuits; Transistors; 18GHz; dual-ILFD; large locking range; low power;

fLanguage

English

Publisher

ieee

Conference_Titel

Millimeter Waves (GSMM), 2012 5th Global Symposium on

Conference_Location

Harbin

Print_ISBN

978-1-4673-1302-5

Type

conf

DOI

10.1109/GSMM.2012.6314054

Filename

6314054