Evolution of Graphics Northbridge Test and Debug Architectures Across Four Generations of AMD ASICs

Author

Margulis, Arie ; Akselrod, David ; Rentschler, Eric ; Ricchetti, Mike

Author_Institution

Adv. Micro Devices Inc., Markham, ON, Canada

Volume

30

Issue

4

fYear

2013

fDate

Aug. 2013

Firstpage

16

Lastpage

25

Abstract

Rapid growth in size and complexity of modern SoCs results in numerous architectural changes in design for test (DFT) and design for debug (DFD). Understanding the challenges and tracking the advances in DFT and DFD (DFx) design and architecture are essential for correct architecture planning of the next generation of SoCs. This paper provides an insight into the evolution of Graphics Northbridge (GNB) DFx architectures across four generations of AMD Application Specific Integrated Circuit (ASIC), including the first AMD fusion accelerated processor unit (APU).

Keywords

computer architecture; design for testability; graphics processing units; integrated circuit design; integrated circuit testing; system-on-chip; AMD ASICs; AMD fusion accelerated processor unit; GNB DFx architectures; SoC; application specific integrated circuit; architecture planning; debug architectures; design for debug; design for test; graphics northbridge test; Computer graphics; Debugging; Discrete Fourier transforms; Network architecture; Network security; Software testing; System-on-chip; APU; DFD; DFT; DFX; Debug;

fLanguage

English

Journal_Title

Design & Test, IEEE

Publisher

ieee

ISSN

2168-2356

Type

jour

DOI

10.1109/MDAT.2013.2274651

Filename

6567961