DocumentCode :
574126
Title :
Sampled-data controller implementation
Author :
Yu Wang ; Leduc, Ryan J.
fYear :
2012
fDate :
27-29 June 2012
Firstpage :
5287
Lastpage :
5293
Abstract :
The setting of this paper is the implementation of timed discrete-event systems (TDES) as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes states, and updates its outputs. In this paper, we establish a formal representation of an SD controller as a Moore synchronous finite state machine (FSM). We describe how to translate a TDES supervisor to a FSM, as well as necessary properties to be able to do so. We discuss how to construct a single centralized controller as well as a set of modular controllers, and show that they will produce equivalent output. We also discuss a flexible manufacturing system (FMS) example and present some FSM translation issues encountered, as well as the FSM version of some of the system´s supervisors.
Keywords :
centralised control; discrete event systems; finite state machines; flexible manufacturing systems; periodic control; sampled data systems; FSM translation; FSM version; Moore synchronous finite state machine; SD controller; TDES supervisor; flexible manufacturing system; formal representation; modular controllers; periodic clock; sampled-data controller implementation; sampled-data controllers; single centralized controller; timed discrete-event systems; Clocks; Closed loop systems; Controllability; Indexes; Manufacturing systems; Synchronization; Vectors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
American Control Conference (ACC), 2012
Conference_Location :
Montreal, QC
ISSN :
0743-1619
Print_ISBN :
978-1-4577-1095-7
Electronic_ISBN :
0743-1619
Type :
conf
DOI :
10.1109/ACC.2012.6314710
Filename :
6314710
Link To Document :
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