Single-Event Cluster Multibit Upsets Due to Localized Latch-Up in a 90 nm COTS SRAM Containing SEL Mitigation Design

Author

Luo Yin-Hong ; Zhang Feng-Qi ; Guo Hong-Xia ; Zhou Hui ; Zheng Li-Sang ; Ji Dong-Mei ; Shen Chen ; Gong Ding ; Hajdas, Wojtek

Author_Institution

Northweat Inst. of Nucl. Technol., Xi´an, China

Volume

61

Issue

4

fYear

2014

fDate

Aug. 2014

Firstpage

1918

Lastpage

1923

Abstract

We report a study on a COTS 90 nm low-power SRAM chip, which is immune to single-event latch-up due to its on-chip latch-up suppression circuit. However, under heavy-ion as well as proton irradiation test, the chip exhibits cluster flips, i.e. flipping of tens of bits due to a single particle strike. We attribute the cluster flips to localized latch-up events that can affect a segment of 32 × 64 bits, which is supported by TCAD simulations. We suggest to further scrutinize the latch-up suppression design, due to its apparent inability to prevent localized latch-ups.

Keywords

SRAM chips; flip-flops; integrated circuit design; low-power electronics; proton effects; radiation hardening (electronics); technology CAD (electronics); SEL mitigation design; TCAD simulations; heavy-ion irradiation; localized latch-up; low-power COTS SRAM chip; on-chip latch-up suppression circuit; proton irradiation test; single-event cluster multibit upsets; size 90 nm; Arrays; Gold; Ions; Protons; Radiation effects; SRAM chips; Cluster multibit upset; current-limiting PMOS; localized latch-up; propagation of potential collapse;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2014.2314722

Filename

6837498