Title :
Comparison of FICDM and Wafer-Level CDM Test Methods
Author :
Jack, Nathan ; Rosenbaum, Elyse
Author_Institution :
Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
The on-chip stresses induced by various charged device model (CDM) test methods are compared at both the package and wafer levels. Test methods studied include field-induced CDM (FICDM), wafer-level CDM (WCDM2), capacitively coupled transmission-line pulsing (CC-TLP), and very fast TLP (VF-TLP). The generated stresses are compared on the basis of voltage monitor readings and integrated circuit (IC) functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics can alter the externally measured FICDM current pulse relative to that delivered internal to the IC, causing miscorrelation with wafer-level testers.
Keywords :
CMOS integrated circuits; failure analysis; integrated circuit testing; transmission lines; wafer level packaging; wafer-scale integration; CC-TLP; FICDM current pulse relative; IC functional failures; VF-TLP; WCDM2; capacitively coupled transmission-line pulsing; charged device model test methods; core circuit failures; field-induced CDM; integrated circuit functional failures; on-chip stresses; package levels; package-related parasitics; very fast TLP; voltage monitor readings; wafer levels; wafer-level CDM; wafer-level CDM test methods; CMOS integrated circuits (ICs); electrostatic discharge (ESD); integrated circuit (IC) testing; transmission-line measurements;
Journal_Title :
Device and Materials Reliability, IEEE Transactions on
DOI :
10.1109/TDMR.2013.2262606
