Extrinsic base resistance optimization in DPSA-SEG SiGe:C HBTs

Author

Canderle, E. ; Chevalier, P. ; Montagné, A. ; Moynet, L. ; Avenier, G. ; Boulenc, P. ; Buczko, M. ; Carminati, Y. ; Rosa, J. ; Gaquière, C. ; Chantre, A.

Author_Institution

STMicroelectron., Crolles, France

fYear

2012

fDate

Sept. 30 2012-Oct. 3 2012

Firstpage

1

Lastpage

4

Abstract

The influence of an additional annealing in the base/emitter module fabrication of state-of-the-art DPSA-SEG SiGe:C HBTs is studied in this paper. The objective of this annealing is to reduce the extrinsic base resistance R_Bx which in previous studies appeared to limit f_MAX of DPSA-SEG SiGe HBTs. TCAD simulations and on-silicon measurements are presented for two different base widths. It is shown that the f_MAX increase brought by R_BX reduction can be traded for a larger f_T. A f_T/f_MAX frequencies couple reaching 320/390 GHz is demonstrated, associated to a CML ring oscillator gate delay time of 2.2 ps.

Keywords

Ge-Si alloys; annealing; carbon; heterojunction bipolar transistors; technology CAD (electronics); CML ring oscillator gate delay time; DPSA-SEG HBT; SiGe:C; TCAD simulations; annealing; base widths; base-emitter module fabrication; extrinsic base resistance optimization; on-silicon measurements; time 2.2 ps; Annealing; Boron; Epitaxial growth; Heterojunction bipolar transistors; Junctions; Logic gates; Resistance; Annealing; Heterojunction bipolar transistors (HBT); Silicon Germanium (SiGe);

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 2012 IEEE

Conference_Location

Portland, OR

ISSN

1088-9299

Print_ISBN

978-1-4673-3020-6

Type

conf

DOI

10.1109/BCTM.2012.6352650

Filename

6352650