A Floating CDAC architecture for high-resolution and low-power SAR A/D converter

Author

Wickmann, Andreas ; Ohnhauser, Frank

Author_Institution

HPA-PA-Energy Solutions, Texas Instrum. Dt. GmbH, Erlangen, Germany

fYear

2012

fDate

24-26 Sept. 2012

Firstpage

5

Lastpage

8

Abstract

A novel analog-to-digital converter (ADC) architecture based on the principle of successive approximation register (SAR) is described. An algorithm is developed, which allows the conversion of high voltage input signals with a low voltage analog core and without a significant attenuation of the input signal. With this technique the Signal-to-Noise Ratio (SNR) can be improved by up to 10 dB at constant power consumption, or the power dissipation of the ADC can be reduced at constant SNR value. Design considerations and simulation results are presented.

Keywords

analogue-digital conversion; digital-analogue conversion; low-power electronics; power consumption; signal processing; ADC architecture; analog-to-digital converter architecture; constant SNR value; floating CDAC architecture; high voltage input signals; high-resolution SAR A/D converter; low voltage analog core; low-power SAR A/D converter; power consumption; power dissipation; signal-to-noise ratio; successive approximation register; Integrated circuits; MOS devices; Signal to noise ratio; ADC; CMOS analog integrated circuits; SAR; analog-to-digital converters; high-resolution; low-noise; low-power; successive approximation register;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference Dresden-Grenoble (ISCDG), 2012 International

Conference_Location

Grenoble

Print_ISBN

978-1-4673-1717-7

Type

conf

DOI

10.1109/ISCDG.2012.6360003

Filename

6360003