Optimum transistor sizing for low-power subthreshold standard cell designs

This paper presents a simple method for standard cell optimization in the subthreshold regime. Through proper dimensioning of the transistor length and width an improved symmetric propagation delay and a reduction in dynamic power consumption compared to conventional CMOS standard cell implementations is achieved. The performance of the presented cells has been verified using logic gate arrays and ring oscillators with high number of stages. The measurement results reasonably agree with simulation data.