Title :
Optimum transistor sizing for low-power subthreshold standard cell designs
Author :
Grimminger, Florian ; Fischer, Georg ; Weigel, Robert ; Kissinger, Dietmar
Author_Institution :
Inst. for Electron. Eng., Univ. of Erlangen-Nuremberg, Erlangen, Germany
Abstract :
This paper presents a simple method for standard cell optimization in the subthreshold regime. Through proper dimensioning of the transistor length and width an improved symmetric propagation delay and a reduction in dynamic power consumption compared to conventional CMOS standard cell implementations is achieved. The performance of the presented cells has been verified using logic gate arrays and ring oscillators with high number of stages. The measurement results reasonably agree with simulation data.
Keywords :
MOSFET; circuit optimisation; logic gates; low-power electronics; oscillators; CMOS standard cell; NMOS transistor; dynamic power consumption reduction; improved symmetric propagation delay; logic gate arrays; low-power subthreshold standard cell designs; optimum transistor sizing; ring oscillators; standard cell optimization method; transistor length; CMOS integrated circuits; CMOS technology; Transistors;
Conference_Titel :
Semiconductor Conference Dresden-Grenoble (ISCDG), 2012 International
Conference_Location :
Grenoble
Print_ISBN :
978-1-4673-1717-7
DOI :
10.1109/ISCDG.2012.6360033
