Hardware/Software Co-design Implementation of On-Chip Backpropagation

Artificial neural networks are a parallel, fault tolerant, robust solution for computational tasks such as associative memories, pattern recognition and function approximation. There are many proposed implementations for artificial neural networks and network´s learning algorithms both in hardware and software. Hardware implementation of learning algorithms are a computational challenge because some constraints as maximum number of neurons and layers, training time, precision, and data representation are difficult to be optimized together. This paper describes a hardware/software co-design implementation of the error-back propagation algorithm on multi-layer perceptron networks. Different types of processors, with different hardware features and goals, were created and the results were analyzed considering mentioned constraints. The results present a hardware/software co-design that allows a large number of neurons and layers, that maintains initial precision without restrictions on data representation. Platform limitations resulted in high execution times but solutions to this problem are also proposed. So the developed hardware proved to be a good alternative considering current hardware implementations of training algorithms and also the mentioned requirements.