Title :
Design and Implementation of 7-bit Pipeline Analog to Digital Converter
Author :
Chouksey, J.S. ; Kanathe, S.
Author_Institution :
Dept. of Electron. & Instrum., SGSITS, Indore, India
Abstract :
Power dissipation of analog and mixed-signal circuits has emerged as a critical design constraint in today´s VLSI systems. This paper presents a multilevel design optimization approach for reducing the power dissipation of a pipelined analog-to-digital converter. This paper describes a 7-b 75-Msample/s analog-to-digital converter fabricated in a 0.18-um CMOS technology. The converter uses pipelined eight-stage architecture with fully differential analog circuits with a full-scale sinusoidal input at 10 MHz. It dissipates 151mW.
Keywords :
CMOS integrated circuits; VLSI; analogue-digital conversion; logic design; mixed analogue-digital integrated circuits; CMOS technology; VLSI systems; frequency 10 MHz; mixed-signal circuits; multilevel design optimization; pipelined analog-to-digital converter; power 151 mW; power dissipation; size 0.18 mum; word length 7 bit; Adders; Analog-digital conversion; CMOS integrated circuits; Computer architecture; Flip-flops; Pipelines; Transient analysis; A/D converter; high-speed; low voltage; pipeline;
Conference_Titel :
Computational Intelligence and Communication Networks (CICN), 2012 Fourth International Conference on
Conference_Location :
Mathura
Print_ISBN :
978-1-4673-2981-1
DOI :
10.1109/CICN.2012.82
