DocumentCode :
580114
Title :
A case for integrated processor-cache partitioning in chip multiprocessors
Author :
Srikantaiah, Shekhar ; Das, Ratan ; Mishra, Akhilesh Kumar ; Das, Chita R. ; Kandemir, Mahmut
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
fYear :
2009
fDate :
14-20 Nov. 2009
Firstpage :
1
Lastpage :
12
Abstract :
Existing cache partitioning schemes are designed in a manner oblivious to the implicit processor partitioning enforced by the operating system. This paper examines an operating system directed integrated processor-cache partitioning scheme that partitions both the available processors and the shared cache in a chip multiprocessor among different multi-threaded applications. Extensive simulations using a set of multiprogrammed workloads show that our integrated processor-cache partitioning scheme facilitates achieving better performance isolation as compared to state of the art hardware/software based solutions. Specifically, our integrated processor-cache partitioning approach performs, on an average, 20.83% and 14.14% better than equal partitioning and the implicit partitioning enforced by the underlying operating system, respectively, on the fair speedup metric on an 8 core system. We also compare our approach to processor partitioning alone and a state-of-the-art cache partitioning scheme and our scheme fares 8.21% and 9.19% better than these schemes on a 16 core system.
Keywords :
cache storage; multi-threading; multiprocessing systems; multiprogramming; operating systems (computers); chip multiprocessor; implicit processor partitioning; integrated processor-cache partitioning scheme; multiprogrammed workload; multithreaded application; operating system; shared cache;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computing Networking, Storage and Analysis, Proceedings of the Conference on
Conference_Location :
Portland, OR
Type :
conf
DOI :
10.1145/1654059.1654066
Filename :
6375563
Link To Document :
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