Title :
Increasing memory miss tolerance for SIMD cores
Author :
Tarjan, David ; Jiayuan Meng ; Skadron, Kevin
Author_Institution :
Dept. of Comput. Sci., Univ. of Virginia, Charlottesville, VA, USA
Abstract :
Manycore processors with wide SIMD cores are becoming a popular choice for the next generation of throughput oriented architectures. We introduce a hardware technique called "diverge on miss" that allows SIMD cores to better tolerate memory latency for workloads with non-contiguous memory access patterns. Individual threads within a SIMD "warp" are allowed to slip behind other threads in the same warp, letting the warp continue execution even if a subset of threads are waiting on memory. Diverge on miss can either increase the performance of a given design by up to a factor of 3.14 for a single warp per core, or reduce the number of warps per core needed to sustain a given level of performance from 16 to 2 warps, reducing the area per core by 35%.
Keywords :
memory architecture; multi-threading; multiprocessing systems; parallel processing; SIMD core; SIMD warp; diverge-on-miss; hardware technique; manycore processor; memory latency; memory miss tolerance; noncontiguous memory access pattern; threads; throughput oriented architecture; workload;
Conference_Titel :
High Performance Computing Networking, Storage and Analysis, Proceedings of the Conference on
Conference_Location :
Portland, OR
DOI :
10.1145/1654059.1654082
