A double data rate 8T-cell SRAM architecture for systems-on-chip

The substantial increase in market demand for handheld devices drives the need for low-power high-speed data access SRAM for systems-on-chip (SoCs). In this paper, we present a novel low-power SRAM architectural design that provides high-noise margin double data rate (DDR) read/write accesses using a conventional 8T-Cell and a partitioned architectural structure consisting of even and odd modules (corresponding to even and odd addresses), which are accessed alternatingly. Write accesses occur at both clock edges such that the even modules are accessed at the rising edge and the odd modules are accessed at the falling edge. Similarly, the read accesses occur at both clock edges such that the even modules are assumed to be evaluated at the rising clock edge, while concurrently the odd modules are pre-charged, and vice versa. We implement a 128-bit × 64-bit SRAM with DDR accesses and an 8T-Cell structure using a standard 0.09μm/1V CMOS TSMC process. Simulation results reveal that our architecture operates with a 1GHz read/write cycle, a data throughput of 2GHz/64-bit, and an average power consumption of 23.4mW.