Effects of scaling a coarse-grain reconfigurable array on power and energy consumption

Author

Hussain, Waqar ; Ahonen, Tapani ; Nurmi, Jari

Author_Institution

Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere, Finland

fYear

2012

fDate

10-12 Oct. 2012

Firstpage

1

Lastpage

5

Abstract

In recent past, we scaled a 4 × 8 processing element (PE) template-based Coarse-Grain Reconfigurable Array (CGRA) to a 4×4, 4×16 and 4×32 PE CGRA and generated matrix-vector multiplication (MVM) accelerators from each one of them. Furthermore, on each of the accelerators, MVM kernels of order N = 4; 8; 16; 32 were mapped. In this paper, we have estimated the power and energy consumption by generating the postfit gate-level netlist of each accelerator for a Field Programmable Gate Array as target platform. Based on our measurements, we have studied the effects of scalability of a CGRA on power and energy consumption.

Keywords

embedded systems; field programmable gate arrays; matrix multiplication; reconfigurable architectures; coarse-grain reconfigurable array; energy consumption; field programmable gate array; matrix-vector multiplication accelerators; postfit gate-level netlist; power consumption; processing element template-based CGRA; Arrays; Energy consumption; Field programmable gate arrays; Logic gates; Power demand; Resource management; Vectors;

fLanguage

English

Publisher

ieee

Conference_Titel

System on Chip (SoC), 2012 International Symposium on

Conference_Location

Tampere

Print_ISBN

978-1-4673-2895-1

Electronic_ISBN

978-1-4673-2894-4

Type

conf

DOI

10.1109/ISSoC.2012.6376372

Filename

6376372