Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation

Hybrid functional verification and debug systems which combine high execution speed of logic emulators and full observability and controllability of software simulators are widely used, but suffer from scalability problem since software simulators cannot handle large and complex System-on-chip (SoC) designs efficiently, restricting their application to only relatively small designs. This paper presents a completely scalable hybrid verification and debug system based on dynamically reconfigurable co-simulation. Unlike existing systems, it allows one or more component logic blocks of a SoC to run on simulator for debugging while rest of the design still runs on emulator. The full design under test (DUT) is run on emulator at near hardware speed for long test sequences, and on error detection one or more logic blocks are transparently switched over to simulation for debugging, initializing the system as a piecewise co-simulator. Logic blocks can be flexibly relocated between simulator and emulator dynamically, without going through time consuming design recompilation phase, allowing designers to quickly debug functional issues. Application of the system to verification of real complex designs shows the effectiveness of our approach.