DocumentCode :
580985
Title :
Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips
Author :
Yeh, Sheng-Han ; Chang, Jia-Wen ; Huang, Tsung-Wei ; Ho, Tsung-Yi
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear :
2012
fDate :
5-8 Nov. 2012
Firstpage :
353
Lastpage :
360
Abstract :
Electrowetting-on-dielectric (EWOD) chips have become the most promising technology to realize pin-constrained digital microfluidic biochips (PDMFBs). In the design flow of EWOD chips, reliability is a critical challenge as it directly affects execution of bioassays. The major factor to degrade chip reliability is the trapped charge problem, which is induced by excessive applied voltage. Nevertheless, to comply with the pin constraint for PDMFBs, signal merging is inevitably involved, and thereby incurring trapped charges due to unawareness of applied voltage. Except for the trapped charge problem, wire routing to accomplish electrical connections increases the design complexity of pin-constrained EWOD chips. Unfortunately, no existing works tackle the problems of excessive applied voltage and wire routing, and thus the resultant chip will have more probabilities to fail during execution or can not be realized because of wire routing problem. In this paper, we present a network-flow based algorithm for reliability-driven pin-constrained EWOD chips with the consideration of voltage issue. Our algorithm not only minimizes the reliability problem induced by signal merging but also provides a comprehensive routing solution for EWOD chip-level designs. The experimental results demonstrate the effectiveness of proposed algorithm on real-life chips.
Keywords :
integrated circuit design; integrated circuit reliability; lab-on-a-chip; microfluidics; bioassays; chip reliability; design complexity; design flow; electrical connections; electrowetting-on-dielectric chips; excessive applied voltage; network-flow based algorithm; pin constraint; pin-constrained digital microfluidic biochips; reliability-driven pin-constrained EWOD chips; signal merging; trapped charge problem; voltage issue; voltage-aware chip-level design; wire routing; Electrodes; Force; Pins; Reliability; Routing; Threshold voltage; Wires;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Type :
conf
Filename :
6386637
Link To Document :
بازگشت